School of Engineering – University of Sao Paulo
Department of Electronic Systems
Cadence University Program Member
Undergraduate level courses in VLSI Design using Cadence tools:
- PSI 3452 Digital and Analog Integrated C Design
- PSI 3551 On-chip Embedded Systems Design
Graduate-level courses in VLSI Design using Cadence tools:
- PSI 5723 Introduction to VLSI Systems Design in CMOS
- PSI 5748 Design of High-Performance VLSI Circuits
Current research projects using Cadence tools:
- Design of CMOS RF/Analog Circuits
This project aims to develop integrated RF-CMOS circuits of different orders. The design methodologies for high-speed CMOS digital ICs developed in the Electronic Systems Department have been useful in the design of RF circuits operating at 2.4 GHz band. Considering the importance of bringing up human resources in this area (CMOS RF Design) in Brazil, effort has been made on the study of RF transmitters and receptors (ultrawide band, UWB), and the analysis of the most important structures for these systems in CMOS standard technologies. The department carries out continuous study and implementation of the functional blocks for these systems, such as Low Noise Amplifiers (LNAs), Frequency Synthesizers, Power Amplifiers, Mixers, Voltage Controlled Oscillators, A/D and D/A Converters, filters and verification tests for each of them.
- Synthesis of Analog ICs at Circuit and System Levels by using Efficient Optimization Methods
The design of analog integrated circuits requires complying several performance specifications, as well as a time specification, in order to avoid compromising the overall design time of mixed signal projects. The traditional design flow for analog integrated circuits is usually accomplished using only hand calculations and adjustments through the use of electrical simulators. In this research, techniques for analog design synthesis for circuit and system level are studied, particularly an optimization algorithm based on Simulated Annealing/Simulated Quenching with a mechanism for using the crossover operator considering multi-objective information. An hybrid algorithm combining the proposed algorithm with Particle Swarm Optimization is also evaluated in order to properly explore the Pareto front. The generality of modern optimization methods allow that variations of the same techniques to be used in circuit level (sizing and biasing of circuit components) and in system level (translation of system specifications to block specifications). Therefore, techniques for the creation of a circuit-level and system-level tool are being developed. In order to validate the proposed algorithms and circuit level tool, circuit-examples will be synthesized in 0.35 _m, 180 nm e 130 nm technology. The synthesized circuits may include Miller amplifiers, complementary folded cascode amplifiers, low noise amplifiers and voltage reference circuits. In system level, syntheses of Gm-C filters are being planned to validate the tool.
- Ultrawide Band Technology for Cancer Detection
One important and promising application of UWB technology is the scanning surface and deeply located structures, as cervix or breast tissues, for cancer diagnosis. This activity has the potential of substituting X-ray mammography and other more invasive methods since, by applying UWB, harmful effects due to long exposure to ionizing radiation are not present. Several circuits as power management block, down converter mixer, A/D and D/A converters are planned in this research.
- Ultra Low Voltage BLE Receiver
Among the Internet of Things (IoT) devices, the RF transceiver is one of the main parts and it is one of the most power hungry circuits. In order to reduce the transceiver power consumption, new communication standards have been proposed for next generation of ultra-low power transceivers, as is the Bluetooth Low Energy (BLE), able to connect a large number of devices, such as personal computers, smartphones and smartwatches. In this context, our work aims to design a Bluetooth BLE (5.0 version) receiver able to operate at only 0.5V of power supply. At this level, the circuit has low power consumption and can be powered by energy harvesting sources or by small battery cells using a high efficiency only step-down DC-DC converter to maximize the circuit lifetime. Due to the low voltage operation, some new design strategies for RF and IF circuits are in development
- SAMPA Chip: the New 32 Channels ASIC for the ALICE TPC and MCH Upgrades
SAMPA is an ASIC designed for the upgrade of read-out front end electronics of the CERN ALICE Time Projection Chamber (TPC) and Muon Chambers (MCH). SAMPA is being developed in a 130 nm CMOS technology with 1.25 V nominal voltage supply and includes 32 channels, with selectable input polarity, and five possible combinations of shaping time and sensitivity. Each channel comprises a Charge Sensitive Amplifier, a semi-Gaussian shaper and a 10-bit ADC, followed by a Digital Signal Processor with several possible configurations of filtering, data compression. The ASIC provides output readout up to 3.5 Gbps via differential high speed serial links.
Dr. Wang Jiang Chau
Department of Electronic Systems Engineering
Av. Prof. Luciano Gualberto, Tr. 3 #158
São Paulo, SP 05508-900 Brazil
Phone: +5511 3091 5257
Fax: +5511 3091 5585
E-mail: jcwang AT lme.usp.br
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Last update: September 12nd, 2017.